Top 2 Engrxiv Papers Today in Engineering


2.032 Mikeys
#1. Bus holding control of running buses in time windows
Konstantinos Gkiotsalitis
This work proposes a periodic bus holding control method where the bus holding times of all running trips are computed simultaneously within each optimization time period; thus, increasing the coordination among running buses to avoid bus bunching. We consider the adverse effects of the bus holding control on the in-vehicle travel times of on-board passengers and formulate holistic bus holding decisions by modeling the bus holding problem as a discrete, nonlinear, constrained optimization problem. Given the computational complexity of the bus holding problem, an alternating minimization approach is introduced for computing the optimal holding times at each optimization instance. The performance of the periodic control method is evaluated against the performance of event-based control methods using 5-month automated vehicle location and automated passenger count data from bus line 1 in Stockholm demonstrating an improvement potential of 5% for the in-vehicle travel times and 11% for the service regularity.
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engrXiv: "Bus holding control of running buses in time windows" - https://t.co/bXXTjNUAJw #engineering
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Sample Sizes : None.
Authors: 1
Total Words: 0
Unqiue Words: 0

2.003 Mikeys
#2. Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores
Karthik Ganesan, Srinivasa Shashank Nuthakki
Existing techniques to ensure functional correctness and hardware trust during pre-silicon verification face severe limitations. In this work, we systematically leverage two key ideas: 1) Symbolic QED, a recent bug detection and localization technique using Bounded Model Checking (BMC); and 2)Symbolic starting states, to present a method that: i) Effectively detects both “difficult” logic bugs and Hardware Trojans, even with long activation sequences where traditional BMC techniques fail; and ii) Does not need skilled manual guidance for writing testbenches, writing design-specific assertions, or debugging spurious counter-examples. Using open-source RISC-V cores, we demonstrate the following: 1. Quick (≤5 minutes for an in-order scalar core and ≤2.5 hours for an out-of-order superscalar core) detection of 100% of hundreds of logic bug and hardware Trojan scenarios from commercial chips and research literature, and 97.9% of “extremal” bugs (randomly-generated bugs requiring ~100,000 activation instructions taken from random test...
more | pdf
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Tweets
engrXiv: "Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores" - https://t.co/5SUO5yJiYF #engineering
Github
None.
Youtube
None.
Other stats
Sample Sizes : [3, 12, 14, 3, 4, 4, 4, 2, 248, 112810248192, 5, 30, 4, 4, 100, 4, 4, 16, 3, 3]
Authors: 2
Total Words: 13852
Unqiue Words: 3725

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