Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications
Recently, the field of deep learning has received great attention by the scientific community and it is used to provide improved solutions to many computer vision problems. Convolutional neural networks (CNNs) have been successfully used to attack problems such as object recognition, object detection, semantic segmentation, and scene understanding. The rapid development of deep learning goes hand by hand with the adaptation of GPUs for accelerating its processes, such as network training and inference. Even though FPGA design exists long before the use of GPUs for accelerating computations and despite the fact that high-level synthesis (HLS) tools are getting more attractive, the adaptation of FPGAs for deep learning research and application development is poor due to the requirement of hardware design related expertise. This work presents a workflow for deep learning mobile application acceleration on small low-cost low-power FPGA devices using HLS tools. This workflow eases the design of an improved version of the SqueezeJet accelerator used for the speedup of mobile-friendly low-parameter ImageNet class CNNs, such as the SqueezeNet v1.1 and the ZynqNet. Additionally, the workflow includes the development of an HLS-driven analytical model which is used for performance estimation of the accelerator. This model can be also used to direct the design process and lead to future design improvements and optimizations.
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Panagiotis G. Mousouliotis (add twitter)
Loukas P. Petrou (add twitter)
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SqueezeNet: AlexNet-level accuracy with 50x fewer parameters
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02/10/19 06:02PM
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Underfox3: Researchers have demonstrated a workflow which eases the mapping of mobile-friendly CNNs onto low-cost low-power small FPGA SoC devices. #DeepLearning https://t.co/My8CODHevY https://t.co/H7ANrYAVe5
arxiv_pop: 2019/02/08 投稿 4位 CV(Computer Vision and Pattern Recognition) Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications https://t.co/hOh5d4um5Y 11 Tweets 3 Retweets 15 Favorites
arxiv_cscv: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications https://t.co/p0MxrGrY3y
arxivml: "Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications", Panagiotis G. Mousouliotis, Louka… https://t.co/kX3GEKZb5s
FunStreets: RT @DSPonFPGA: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications https://t.co/5umzle9pFl
DSPonFPGA: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications https://t.co/5umzle9pFl
marsee101: RT @arxiv_cscv: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications https://t.co/p0MxrGrY3y
arxiv_cs_LG: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications. Panagiotis G. Mousouliotis and Loukas P. Petrou https://t.co/z0HExWxtrF
arxiv_cscv: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications https://t.co/p0MxrGrY3y
BrundageBot: Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications. Panagiotis G. Mousouliotis and Loukas P. Petrou https://t.co/4DrDq2uJaW
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